1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit device at-speed structural testing techniques and, more specifically, to a system and method for automatically generating test patterns for an at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count.
2. Description of the Related Art
An automatic test pattern generator (ATPG) is a computer system that uses software tools to generate test patterns (i.e., input/test sequences) that, when applied to a level sensitive scan design (LSSD)), enable testers to distinguish between circuit behavior that is desirable and circuit behavior that is indicative of design or manufacturing defects. At-speed structural testing techniques use such ATPGs to select and generate test patterns when testing for defects, such as high impedance shorts, in-line resistance or cross-talk between signals, which are only apparent when the integrated circuit device is run at speed.
Unfortunately, during at-speed testing, misalignment of clock signals can occur as signals are exchanged between different circuit partitions, e.g., clock domains, power domains, etc. To prevent such asynchronous captures across clock domains, functional clock domains are typically tested one domain at a time (see U.S. Patent Application Publication No. US 2008/0222472 of Grise et al., which is incorporated herein by reference). As a result, test pattern count can be high, especially for large domains. Therefore, there is a need in the art for a method for automatically generating test patterns for an at-speed structural test of an integrated circuit device that reduces test pattern count. Moreover, as automatic test generation for a large domain proceeds, a knee in the coverage curve is observed after a point, beyond which each additional pattern does not detect a large number of faults. The problem being solved in the present invention is how to cut off test generation for large domains in ASST, such that the highest test coverage may be achieved while remaining below a test pattern budget.